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wide supply range, micropower, rail-to-rail instrumentation amplifier data sheet ad8420 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2012 analog devices, inc. all rights reserved. features maximum supply current: 80 a minimum cmrr: 100 db drives heavy capacitive loads: ~700 pf rail-to-rail output input voltage range goes below ground gain set with 2 external resistors can achieve low gain drift at any gain very wide power supply range single supply: 2.7 v to 36 v dual supply: 2.7 v to 18 v bandwidth (g = 100): 2.5 khz input voltage noise: 55 nv/hz high dc precision maximum offset voltage: 125 v maximum offset drift: 1 v/ c maximum differential input voltage: 1 v 8-lead msop package applications bridge amplifiers pressure measurement medical instrumentation portable data acquisition multichannel systems pin configuration nc 1 +in 2 ?in 3 ?v s 4 v out 8 fb 7 ref 6 +v s 5 ad8420 top view (not to scale) + ? ? + 09945-001 figure 1. table 1. instrumentation amplifiers by category 1 general purpose zero drift military grade low power digital gain ad8221 , ad8222 ad8231 ad620 ad8420 ad8250 ad8220 , ad8224 ad8290 ad621 ad8235 , ad8236 ad8251 ad8226 , ad8227 ad8293 ad524 ad627 ad8253 ad8228 ad8553 ad526 ad8226 , ad8227 ad8231 ad8295 , ad8224 ad8556 AD624 ad623 ad8557 ad8223 1 see www.analog.com for the latest instrumentation amplifiers. general description the ad8420 is a low cost, micropower, wide supply range, instrumentation amplifier with a rail-to-rail output and a novel architecture that allows for extremely flexible design. it is optimized to amplify small differential voltages in the presence of large common-mode signals. the ad8420 is based on an indirect current feedback architecture that gives it an excellent input common-mode range. unlike conventional instrumentation amplifiers, the ad8420 can easily amplify signals at or even slightly below ground without requiring dual supplies. the ad8420 has rail-to-rail output, and the output voltage swing is completely independent of the input common- mode voltage. single-supply operation, micropower current consumption, and rail-to-rail output swing make the ad8420 ideal for battery- powered applications. its rail-to-rail output stage maximizes dynamic range when operating from low supply voltages. dual- supply operation (15 v) and low power consumption make the ad8420 ideal for a wide variety of applications in medical or industrial instrumentation. the ad8420 is available in an 8-lead msop package. performance is specified over the full temperature range of ?40c to +85c, and the part is operational from ?40c to +125c.
ad8420 data sheet rev. 0 | page 2 of 28 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? pin configuration............................................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? absolute maximum ratings............................................................ 7 ? thermal resistance ...................................................................... 7 ? esd caution.................................................................................. 7 ? pin configuration and function descriptions............................. 8 ? typical performance characteristics ............................................. 9 ? theory of operation ...................................................................... 19 ? architecture................................................................................. 19 ? setting the gain .......................................................................... 19 ? gain accuracy ............................................................................ 20 ? input voltage range................................................................... 20 ? input protection ......................................................................... 20 ? layout .......................................................................................... 21 ? driving the reference pin......................................................... 21 ? input bias current return path ............................................... 22 ? radio frequency interference (rfi)........................................ 22 ? output buffering ........................................................................ 23 ? applications information .............................................................. 24 ? ad8420 in electrocardiography (ecg).................................. 24 ? classic bridge circuit ................................................................ 25 ? 4 ma to 20 ma single-supply receiver .................................. 25 ? outline dimensions ....................................................................... 26 ? ordering guide .......................................................................... 26 ? revision history 3 /12revision 0: initial version
data sheet ad8420 rev. 0 | page 3 of 28 specifications +v s = + 5 v, ?v s = 0 v, v ref = 0 v, v +in = 0 v, v ?in = 0 v, t a = 25c, g = 1 to 1000, r l = 20 k, specifications referred to input, unless otherwise noted. all tabl e 2 limits are valid from v s = 3 v to v s = 5 v, unless otherwise specified. table 2. parameter test conditions/comments min typ max unit common-mode rejection ratio (cmrr) v cm = 0 v to 2.7 v cmrr dc to 60 hz 100 db cmrr at 1 khz 100 db noise voltage noise spectral density f = 1 khz, v diff 100 mv 55 nv/hz peak to peak f = 0.1 hz to 10 hz, v diff 100 mv 1.5 v p-p current noise spectral density f = 1 khz 80 fa/hz peak to peak f = 0.1 hz to 10 hz 3 pa p-p voltage offset offset v s = 3 v to v s = 5 v 125 v v s = 5 v 150 v average temperature coefficient t a = ?40c to +85c 1 v/c offset rti vs. supply (psr) v s = 2.7 v to 5 v 86 db inputs valid for ref and fb pair, as well as +in and ?in input bias current 1 t a = +25c 20 27 na t a = +85c 24 na t a = ?40c 30 na average temperature coefficient t a = ?40c to +85c 30 pa/c input offset current t a = +25c 1 na t a = +85c 1 na t a = ?40c 1 na average temperature coefficient t a = ?40c to +85c 0.5 pa/c input impedance differential 130||2 m||pf common mode 1000||2 m||pf differential input operating voltage t a = C40c to +85c ?1 +1 v input operating voltage (+in, ?in, ref, or fb) t a = +25c ?v s ? 0.15 +v s ? 2.2 v t a = +85c ?v s ? 0.05 +v s ? 1.8 v t a = C40c ?v s ? 0.2 +v s ? 2.7 v dynamic response small signal ?3 db bandwidth g = 1 250 khz g = 10 25 khz g = 100 2.5 khz g =1000 0.25 khz settling time 0.01% v s = 5 v g = 1 ?1 v to +1 v output step 3 s g = 10 ?4.5 v to +4.5 v output step 130 s g = 100 ?4.5 v to +4.5 v output step 1 ms slew rate 1 v/s
ad8420 data sheet rev. 0 | page 4 of 28 parameter test conditions/comments min typ max unit gain 2 g = 1 + (r2/r1) gain range 1 1000 v/v gain error g = 1 v out = 0.1 v to 1.1 v, v ref = 0.1 v 0.02 % g = 10 to 1000 v out = 0.2 v to 4.8 v 0.05 0.1 % gain vs. temperature t a = ?40c to +85c 10 ppm/c output output swing v s = 5 v, r l = 10 k to midsupply v s = 5 v, r l = 20 k to ground t a = +25c ?v s + 0.1 +v s ? 0.15 v t a = +85c ?v s + 0.1 +v s ? 0.2 v t a = ?40c ?v s + 0.1 +v s ? 0.15 v short-circuit current 10 ma power supply operating range single-supply operation 3 2.7 36 v quiescent current v s = 5 v t a = +25c 55 70 80 a t a = +85c 95 a t a = ?40c 65 a temperature range specified ?40 +85 c operational 4 ?40 +125 c 1 the input stage uses pnp transi stors; therefore, input bias curre nt always flows out of the part. 2 for g > 1, errors from external resistor r1 and external resistor r2 should be considered in addition to these specifications, including error from fb pin bias current. 3 minimum supply voltage indicated for v +in , v ?in , and v ref = 0 v. 4 see the typical performance characteristics section for operation be tween 85c and 125c.
data sheet ad8420 rev. 0 | page 5 of 28 +v s = +15 v, ?v s = ?15 v, v ref = 0 v, t a = 25c, g = 1 to 1000, r l = 20 k, specifications referred to input, unless otherwise noted. table 3. parameter test conditions/comments min typ max unit common-mode rejection ratio (cmrr) v cm = ?10 v to +10 v cmrr dc to 60 hz 100 db cmrr at 1 khz 100 db noise voltage noise spectral density f = 1 khz, v diff 100 mv 55 nv/hz peak to peak f = 0.1 hz to 10 hz, v diff 100 mv 1.5 v p-p current noise spectral density f = 1 khz 80 fa/hz peak to peak f = 0.1 hz to 10 hz 3 pa p-p voltage offset offset v s = 15 v 1 250 v average temperature coefficient t a = ?40c to +85c 1 v/c offset rti vs. supply (psr) v s = 15 v 100 db inputs valid for ref and fb pair, as well as +in and ?in input bias current 2 t a = +25c 20 27 na t a = +85c 24 na t a = ?40c 30 na average temperature coefficient t a = ?40c to +85c 30 pa/c input offset current t a = +25c 1 na t a = +85c 1 na t a = ?40c 1 na average temperature coefficient t a = ?40c to +85c 0.5 pa/c input impedance differential 130||3 m||pf common mode 1000||3 m||pf differential input operating voltage t a = ?40c to +85c ?1 1 v input operating voltage (+in, ?in, ref, or fb) t a = +25c ?v s ? 0.15 +v s ? 2.2 v t a = +85c ?v s ? 0.05 +v s ? 1.8 v t a = ?40c ?v s ? 0.2 +v s ? 2.7 v dynamic response small signal ?3 db bandwidth g = 1 250 khz g = 10 25 khz g = 100 2.5 khz g =1000 0.25 khz settling time 0.01% g = 1 ?1 v to +1 v output step 3 s g = 10 ?5 v to +5 v output step 130 s g = 100 ?5 v to +5 v output step 1 ms slew rate 1 v/s gain 3 g = 1 + (r2/r1) gain range 1 1000 v/v gain error g = 1 v out = 1 v 0.02 % g = 10 to 1000 v out = 10 v 0.05 0.1 % gain vs. temperature t a = ?40c to +85c 10 ppm/c
ad8420 data sheet rev. 0 | page 6 of 28 parameter test conditions/comments min typ max unit output output swing r l = 20 k to ground t a = +25c ?v s + 0.13 +v s ? 0.2 v t a = +85c ?v s + 0.15 +v s ? 0.23 v t a = C40c ?v s + 0.11 +v s ? 0.16 v short-circuit current 10 ma power supply operating range dual-supply operation 4 2.7 18 v quiescent current v s = 15 v t a = +25c 70 85 100 a t a = +85c 120 a t a = ?40c 90 a temperature range specified ?40 +85 c operational 5 ?40 +125 c 1 see the section for the offset voltage vs. supply. typical performance characteristics 2 the input stage uses pnp transi stors; therefore, input bias curre nt always flows out of the part. 3 for g > 1, errors from external resistor r1 and external resistor r2 should be considered in addition to these specifications, including error from fb pin bias current. 4 minimum positive supply voltage indicated for v +in , v ?in , and v ref = 0 v. with v +in , v ?in , and v ref = ?v s , minimum supply is 1.35 v. 5 see the typical performance characteristics section for operation be tween 85c and 125c.
data sheet ad8420 rev. 0 | page 7 of 28 absolute maximum ratings table 4. parameter rating supply voltage 18 v output short-circuit current indefinite maximum voltage at ?in or +in ?v s + 40 v minimum voltage at ?in or +in ?v s ? 0.5 v maximum voltage at ref or fb +v s + 0.5 v minimum voltage at ref or fb ?v s ? 0.5 v storage temperature range ?65c to +150c esd human body model 2.5 kv charge device model 1.5 kv machine model 0.1 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for a device in free air. table 5. package ja unit 8-lead msop, 4-layer jedec board 135 c/w esd caution
ad8420 data sheet rev. 0 | page 8 of 28 pin configuration and fu nction descriptions nc 1 +in 2 ?in 3 ?v s 4 v out 8 fb 7 ref 6 +v s 5 a d8420 top view (not to scale) + ? ? + 09945-002 figure 2. pin configuration table 6. pin function descriptions pin no. mnemonic description 1 nc this pin is not connected internally. for best cmrr vs. frequency and leakage performance, connect this pin to negative supply. 2 +in positive input. 3 ?in negative input 4 ?v s negative supply. 5 +v s positive supply. 6 ref reference input. 7 fb feedback input. 8 v out output.
data sheet ad8420 rev. 0 | page 9 of 28 typical performance characteristics t = 25c, +v s = 5 v, r l = 20 k, unless otherwise noted. 700 600 500 400 300 200 100 0 ?150 ?100 ?50 0 50 100 150 number of hits v os (v) mean: ?34.8195 sd: 31.3406 09945-003 figure 3. typical distributi on of input offset voltage 700 600 500 400 300 200 100 0 25 24 23 22 21 20 number of hits positive bias current (na) mean: 22.6643 sd: 0.6058 0 9945-004 figure 4. typical distribution of input bias current 1200 1000 800 600 400 200 0 ?0.9 ?0.6 ?0.3 0 0.3 0.6 0.9 number of hits offset current (na) mean: 0.000646761 sd: 0.111551 09945-005 figure 5. typical distribution of input offset current 700 600 500 400 300 200 100 0 10 8 6 4 2 0 number of hits cmrr, 15v (v/v) 09945-008 mean: 4.63764 sd: 1.09498 figure 6. typical distribution of cmrr number of hits g m2 positive bias current (na) 09945-006 700 600 500 400 300 200 100 0 25 24 23 22 21 20 mean: 22.706 sd: 0.615728 figure 7. typical distribution of ref, fb bias current 1200 1000 800 600 400 200 0 ?0.9 ?0.6 ?0.3 0 0.3 0.6 0.9 number of hits g m2 offset current (na) 09945-007 mean: 0.00144205 sd: 0.112088 figure 8. typical distribution of ref, fb offset current
ad8420 data sheet rev. 0 | page 10 of 28 3.0 2.5 2.0 1.5 1.0 0.5 0 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?5 0 5 10 15 20 25 30 35 40 output voltage (v) input current (ma) input voltage (v) v s = +5v g = 1 v out i in 09945-309 figure 9. input overvoltage performance, g = 1 3 2 1 0 ?1 ?2 ?3 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?20 ?15 ?10 ?5 0 5 10 15 20 25 output voltage (v) input current (ma) input voltage (v) v s = 15v g = 1 v out i in 09945-310 figure 10. input overvoltage performance, g = 1, v s = 15 v 6 5 4 3 2 1 0 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?5 0 5 10 15 20 25 30 35 40 output voltage (v) input current (ma) input voltage (v) v s = 5v g = 100 v out i in 09945-311 figure 11. input overvoltage performance, g = 100 15 10 5 0 ?5 ?10 ?15 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?20 ?15 ?10 ?5 0 5 10 15 20 25 output voltage (v) input current (ma) input voltage (v) v s = 15v g = 100 v out i in 09945-312 figure 12. input overvoltage performance, g = 100, v s = 15 v 15 10 5 0 ?5 ?10 ?20 ?15 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 input common-mode voltage (v) output voltage (v) 0.0v, +12.8v 0.0v, ?15.1v ?1.0v, +12.3v ?1.0v, ?14.6v +1.0v, ?14.6v +1.0v, +12.3v 09945-313 figure 13. input common-mode voltage vs. output voltage, g = 1, v s = 15 v 3.0 2.5 2.0 1.5 1.0 0.5 ?0.5 0 ?0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 input common-mode voltage (v) output voltage (v) +4mv, +2.8v +4mv, ?0.1v +1.0v, +0.4v +1.0v, +2.3v 09945-314 figure 14. input common-mode voltage vs. output voltage, g = 1, v s = 5 v
data sheet ad8420 rev. 0 | page 11 of 28 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?0.5 1.4 3.23.02.8 2.62.4 2.22.01.81.6 input common-mode voltage (v) output voltage (v) v ref = 2.5v r l = 10k ? to midsupply +2.5v, ?0.1v +3.03v, +0.16v +3.03v, +2.46v +2.5v, +2.8v +1.5v, +0.4v +1.5v, +2.3v 09945-315 figure 15. input common-mode voltage vs. output voltage, g = 1, v s = 5 v, v ref = 2.5 v 0.6 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.1 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 input common-mode voltage (v) output voltage (v) +4mv, +0.5v +4mv, ?0.1v +0.6v, +0.2v 09945-316 figure 16. input common-mode voltage vs. output voltage, g = 1, v s = 2.7 v 20 15 10 5 0 ?5 ?10 ?15 ?20 ?20 20 15 10 50 ?5 ?10 ?15 input common-mode voltage (v) output voltage (v) ?14.9v, +12.7v ?14.9v, ?15.0v 0.0v, ?15.1v 0.0v, +12.8v +14.8v, +12.7v +14.8v, ?15.0v 09945-317 figure 17. input common-mode voltage vs. output voltage, g = 100, v s = 15 v 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?0.5 5.55.0 4.5 3.5 2.5 4.0 3.0 2.01.51.0 00.5 input common-mode voltage (v) output voltage (v) +44mv, +2.8v +44mv, ?0.1v +4.8v, +2.78v +4.8v, ?80mv 09945-318 figure 18. input common-mode voltage vs. output voltage, g = 100, v s = 5 v 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?0.5 5.55.0 4.5 3.5 2.5 4.0 3.0 2.01.51.0 00.5 input common-mode voltage (v) output voltage (v) +86mv, +2.79v +86mv, ?90mv +2.5v, +2.8v +2.5v, ?0.1v +4.8v, +2.79v +4.8v, ?90mv 09945-319 figure 19. input common-mode voltage vs. output voltage, g = 100, v s = 5 v, v ref = 2.5 v 0.6 0.5 0.4 0.3 0.2 0.1 0 ?0.1 ?0.2 ?0.5 3.0 2.5 2.0 1.5 1.0 00.5 input common-mode voltage (v) output voltage (v) +29mv, +0.5v +29mv, ?0.1v +2.53v, +0.49v +2.53v, ?90mv 09945-320 figure 20. input common-mode voltage vs. output voltage, g = 100, v s = 2.7 v
ad8420 data sheet rev. 0 | page 12 of 28 40 35 30 25 20 15 10 5 ?2.0 0 3.0 2.5 2.0 1.5 1.0 0.5 input bias current (na) common-mode voltage (v) 09945-019 +2.7v i bias (+in) i bias (?in) ?0.2v figure 21. input bias current vs. common-mode voltage 400 ?400 ?300 ?200 ?100 0 100 200 300 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 input bias current (na) differential input voltage (v) 09945-020 i bias (+in) i bias (?in) specified performance range figure 22. input bias current vs. differential input voltage, v s = 15 100 0 20 40 60 80 0.1 1 10 100 1k 10k 100k psrr (db) frequency (hz) gain = 1000 bandwidth limit gain = 100 gain = 10 gain = 1 09945-500 figure 23. psrr vs. frequency on 5 v supply 120 0 20 40 60 80 100 0.1 1 10 100 1k 10k 100k positive psrr (db) frequency (hz) gain = 1000 bandwidth limit gain = 100 gain = 10 gain = 1 09945-323 v s = 15v figure 24. positive psrr vs. frequency, rti, v s = 15 v 120 0 20 40 60 80 100 0.1 1 10 100 1k 10k 100k negative psrr (db) frequency (hz) gain = 1000 gain = 100 gain = 10 gain = 1 09945-324 bandwidth limit v s = 15v figure 25. negative psrr vs. frequency, rti, v s = 15 v 70 ?30 ?20 ?10 0 10 20 30 40 50 60 1 10 100 1k 10k 100k 1m gain (db) frequency (hz) 09945-023 v s = 15v gain = 1000 gain = 100 gain = 10 gain = 1 figure 26. gain vs. frequency
data sheet ad8420 rev. 0 | page 13 of 28 70 ?30 ?20 ?10 0 10 20 30 40 50 60 1 10 100 1k 10k 100k 1m gain (db) frequency (hz) 09945-024 v s = 2.7v gain = 1000 gain = 100 gain = 10 gain = 1 figure 27. gain vs. frequency, 2.7 v single supply 140 120 0 20 40 60 80 100 0.1 1 10 100 1k 10k 100k cmrr (db) frequency (hz) gain = 1000 gain = 100 gain = 10 gain = 1 09945-327 bandwidth limit v s = 15v figure 28. cmrr vs. frequency, rti, v s = 15 v 140 120 0 20 40 60 80 100 0.1 1 10 100 1k 10k 100k cmrr (db) frequency (hz) gain = 1000 gain = 100 gain = 10 gain = 1 09945-328 v s = 15v figure 29. cmrr vs. frequency, rti, 1 k source imbalance, v s = 15 v 120 0 20 40 60 80 100 01 0.9 0.80.7 0.60.50.4 0.3 0.20.1 cmrr (db) differential input voltage (v) . 0 v s = 15v v cm = 10v 09945-329 figure 30. cmrr vs. diffe rential input voltage ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 supply current (a) temperature (c) 09945-027 20 30 40 50 60 70 80 90 100 110 120 v s = 5v figure 31. supply current vs. temperature, v s = +5 v 30 0 250 200 150 100 50 0 ?50 5 10 15 20 25 ?40 125 11095 80 65 50 35 20 5 ?10?25 bias current (na) offset current (pa) temperature (c) offset current ?in bias current +in bias current 09945-331 figure 32. input bias current and input offset current vs. temperature
ad8420 data sheet rev. 0 | page 14 of 28 30 0 200 150 100 50 0 ?50 ?100 5 10 15 20 25 ?40 125 11095 806550 35 20 5 ?10?25 bias current (na) offset current (pa) temperature (c) offset current ?in bias current +in bias current 09945-332 figure 33. fb, ref bias current and fb , ref offset current vs. temperature 1000 ?1000 ?800 ?600 ?400 ?200 0 200 400 600 800 ?40 80 6550 3520 5 ?10 ?25 gain error (v/v) temperature (c) part a v in = 1v v s = 15v part b 09945-333 representative data normalized to 25oc figure 34. gain error vs. temperature, g = 1, v in = 1 v, v s = 15 v 1000 ?1000 ?800 ?600 ?400 ?200 0 200 400 600 800 ?40 80 6550 3520 5 ?10 ?25 gain error (v/v) temperature (c) part a v in = 0.1v v s = 15v part b 09945-334 representative data normalized to 25oc figure 35. gain error vs. temperature, g = 1, v in = 0. 1 v, v s = 15 v 400 ?400 ?300 ?200 ?100 0 100 200 300 ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 offset voltage (v) temperature (c) 09945-031 normalized to 25c figure 36. offset drift ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 cmrr (v/v) temperature (c) 09945-032 ?4 5 4 3 2 1 0 ?1 ?2 ?3 part a: 0.024ppm/c part b: 0.038ppm/c representative data normalized at 25c v s = 15v figure 37. cmrr vs. temperature, g = 1, v s = 15 v + v s ?v s +0.3 +0.2 +0.1 ?0.3 ?0.2 ?0.1 22 18161210 864 output voltage swing (v) referred to supply voltages supply voltage (v s ) 0 ?40c +25c +85c +125c r l = 20k ? 09945-035 figure 38. output voltage swing vs. supply voltage, r l = 20 k
data sheet ad8420 rev. 0 | page 15 of 28 + v s ?v s +0.6 +0.8 +0.4 +0.2 ?0.6 ?0.8 ?0.4 ?0.2 1k 10k 100k 1m output voltage swing (v) referred to supply voltages load resistance ( ? ) 09945-338 ?40c +25c +85c +125c v s = 5v v ref = 2.5v figure 39. output voltage swing vs. load resistance, v s = 5 v + v s ?v s +0.6 +0.8 +0.4 +0.2 ?0.6 ?0.8 ?0.4 ?0.2 0.1 1 output voltage swing (v) referred to supply voltages output current (ma) 09945-501 ?40c +25c +85c +125c v s = 5v v ref = 2.5v figure 40. output voltage swing vs. load resistance, v s = 5 v 15 10 5 0 ?5 ?10 ?15 1k 10k 100k 1m output voltage swing (v) load resistance ( ? ) ?40c +25c +85c +125c 09945-339 figure 41. output voltage swing vs. load resistance, v s = 15 v + v s ?v s ?0.2 ?0.4 ?0.6 ?0.8 +0.8 +0.6 +0.4 +0.2 0.1 1 output voltage swing (v) referred to supply voltages output current (ma) ?40c +25c +85c +125c 09945-340 figure 42. output voltage swing vs. output current, v s = 15 1k 2k 100 20 0.1 1 10 100 1k 10k 100k noise (nv/ hz) frequency (hz) 09945-042 gain = 100 gain = 10 gain = 1 figure 43. voltage noise spectral density vs. frequency, rti 0 9945-043 0.4v/div 1s/div figure 44. 0.1 hz to 10 hz rti voltage noise, g = 1
ad8420 data sheet rev. 0 | page 16 of 28 1k 100 10 1 10 100 100k 10k 1k noise (fa/ hz) frequency (hz) 09945-348 figure 45. current noise spectral density vs. frequency 0 9945-147 1.5pa/div 1s/div figure 46. 0.1 hz to 10 hz current noise 30 0 3 6 9 12 15 18 21 24 27 1 10 100 1k 10k 100k 1m output voltage (v p-p) frequency (hz) 09945-148 v s = 15v, g = 15v/v v s = +5v, g = 5v/v figure 47. large signal frequency response 0.02%/div 1v/div 20s/div v s = 5v 1.78s to 0.1% 3.31s to 0.01% 09945-149 figure 48. large signal pulse response and settling time, g = 1 0.02%/div 4.5v/div 200s/div v s = 5v 67s to 0.1% 138s to 0.01% 09945-150 figure 49. large signal pulse response and settling time, g = 10 0.02%/div 4.5v/div 20ms/div v s = 5v 600ms to 0.1% 1.04ms to 0.01% 09945-151 figure 50. large signal pulse response and settling time, g = 100
data sheet ad8420 rev. 0 | page 17 of 28 09945-051 20mv/div 4s/div figure 51. small signal pulse response, g = 1, r l = 20 k, c l = 100 pf 09945-052 20mv/div 20s/div figure 52. small signal pulse response, g = 10, r l = 20 k, c l = 100 pf 09945-053 20mv/div 200s/div figure 53. small signal pulse response, g = 100, r l = 20 k, c l = 100 pf 09945-054 20mv/div 2ms/div figure 54. small signal pulse response, g = 1000, r l = 20 k, c l = 100 pf 0 9945-055 20mv/div 5s/div no load 220pf 470pf 780pf figure 55. small signal response with various capacitive loads, g = 1, r l = 04 35 30 2520 15 10 5 supply current (a) supply voltage (v) 09945-057 50 90 85 80 75 70 65 60 55 0 figure 56. supply current vs. supply voltage
ad8420 data sheet rev. 0 | page 18 of 28 6 03 322824201612 84 offset voltage (v) supply voltage (v) 09945-502 ?200 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 90 tested with dual supplies centered at 0v figure 57. offset voltage vs. supply voltage
data sheet ad8420 rev. 0 | page 19 of 28 theory of operation +in ?in g m1 i2 i1 i3 + ? +v s ?v s +v s ?v s +v s ?v s r2 r1 v out fb ref ad8420 09945-058 g m2 esd protection a + ? v b esd protection figure 58. simplified schematic architecture the ad8420 is based on an indirect current feedback topology consisting of three amplifiers: two matched transconductance amplifiers that convert voltage to current and one integrator amplifier that converts current to voltage. for the ad8420 , assume that all initial voltages and currents are zero until a positive differential voltage is applied between the inputs, +in and ?in. transconductance amplifier g m1 converts this input voltage into a current, i1. because the voltage across g m2 is initially zero, i2 is zero and i3 equals i1. i3 is integrated to the output, making the output voltage, v out , increase. this voltage continues to increase until the same differ- ential input voltage across the inputs of g m1 is replicated across the inputs of g m2 , generating a current (i2) equal to i1. this reduces the difference current i3 to zero so that the output remains at a stable voltage. the gain in the configuration shown in figure 58 is set by r2 and r1. in traditional instrumentation amplifiers, the input common- mode voltage can limit the available output swing, typically depicted in a hexagon plot. because the ad8420 converts the input differential signals to current, this limit does not apply. this is particularly important when amplifying a signal with a common- mode voltage near one of the supply rails. to improve robustness and ease of use, the ad8420 includes overvoltage protection on its inputs. this protection scheme allows wide differential input voltages without damaging the part. setting the gain the transfer function of the ad8420 is v out = g ( v +in ? v ?in ) + v ref where: r1 r2 g += 1 table 7. suggested resistors for various gains, 1% resistors r1 (k) r2 (k) gain none short 1.00 49.9 49.9 2.00 20 80.6 5.03 10 90.9 10.09 5 95.3 20.06 2 97.6 49.8 1 100 101 1 200 201 1 499 500 1 1000 1001 while the ratio of r2 to r1 sets the gain, the designer determines the absolute value of the resistors. larger values reduce power consumption and output loading; smaller values limit the fb input bias current and offset current error. for best output swing and distortion performance, keep (r1 + r2) || r l 20 k. a method that allows large value feedback resistors while limiting fb bias current error is to place a resistor of value r1 || r2 in series with the ref terminal, as shown in figure 59 . at higher gains, this resistor can simply be the same value as r1. ad8420 +in ?in ref fb v out g = 1 + r2 r1 i b + i b ? v ref r1 r2 r1 || r2 + ? i b r i b f 09945-059 figure 59. cancelling out error from fb input bias current
ad8420 data sheet rev. 0 | page 20 of 28 gain accuracy unlike most instrumentation amplifiers, the relative match of the two gain setting resistors determines the gain accuracy of the ad8420 rather than a single resistor. for example, if two resistors have exactly the same absolute error, there is no error in gain. conversely, two 1% resistors can cause approximately 2% maximum gain error at high gains. temperature coefficient mismatch of the gain setting resistors increases the gain drift of the instrumentation amplifier circuit. because these external resistors do not have to match any on-chip resistors, resistors with good tc tracking can achieve excellent gain drift. when the differential voltage at the inputs approaches the differential input limit, the diodes start to conduct, limiting the voltage seen by the inputs. this can look like increased gain error at large differential inputs. performance of the ad8420 is specified for 1 v differential from ?40c to +85c. ? however, at higher temperatures, the reduced forward voltage of the diodes limits the differential input to a smaller voltage. figure 60 tracks 1% error across the operating temperature range to show the effect of temperature on the input limit. ?40 ?25 ?10 5 20 35 50 65 80 95 110 125 maximum input voltage (1% error) temperature (c) 09945-503 0 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 positive voltage negative voltage v s = 15v figure 60. differential input limit vs. temperature input voltage range the allowed input range of the ad8420 is much simpler than traditional architectures. for the transfer function of the ad8420 to be valid, the input voltage should follow two rules: x keep the differential input voltage within 1 v. x keep the voltage on the +in, ?in, ref, and fb pins in the specified input voltage range. because the output swing is completely independent of the input common-mode voltage, there are no hexagonal figures or complicated formulas to follow, and no limitation for the output swing the amplifier has for input signals with changing common mode. input protection the current into the ad8420 inputs is limited internally. this ensures that the diodes that limit the differential voltage seen by the internal amplifier do not draw excessive current when they turn on. the part can handle large differential input voltages, regardless of the amount of gain applied, without damage. as a result, the ad8420 inputs are protected from voltages beyond the positive rail. if voltages beyond the negative rail are expected, external protection must be used. keep all of the ad8420 terminals within the voltage range specified in the absolute maximum ratings section. all terminals of the ad8420 are protected against esd. input voltages beyond the rails for applications that require protection beyond the negative rail, one option is to use an external resistor in series with each input to limit current during overload conditions. in this case, size the resistors to limit the current into the ad8420 to 6 ma. r protect ( negative supply ? v in )/6 ma although the ad8420 inputs must still be kept within the ?v s + 40 v limitation, the i r drop across the protection resistor increases the protection on the positive side to approximately (40 v + negative supply ) + 300 a r protect an alternate protection method is to place diodes at the ad8420 inputs to limit voltage and resistors in series with the inputs to limit the current into these diodes. to keep input bias current at a minimum for normal operation, use low leakage diode clamps, such as the bav199. the ad8420 also combines well with tvs diodes, such as the ptvsxs1ur. simple method alternate method ad8420 r protect r protect r protect r protect v in+ + ? v in? v in+ v in? + ? +v s ad8420 ?v s +v s ?v s + v s ?v s +v s ?v s i + ? + ? 09945-160 figure 61. protection for voltages beyond the rails large differential input voltage the ad8420 is able to handle large differential input voltage without damage to the part. refer to figure 9 , figure 10 , figure 11 , and figure 12 for overvoltage performance. the ad8420 differential voltage is internally limited with diodes to 1 v. if this limit is exceeded, the diodes start to conduct and draw current, as shown in figure 22 . this current is limited internally to a value that is safe for the ad8420 , but if the input current cannot be tolerated in the system, place resistors in series with each input with the following value: t ma diff protect i v r v1 2 1
data sheet ad8420 rev. 0 | page 21 of 28 reference layout the output voltage of the ad8420 is developed with respect to the potential on the reference terminal. take care to tie ref to the appropriate local ground. the differential voltage at the inputs is reproduced between the ref and fb pins; therefore, it is important to set v ref so that the voltage at fb does not exceed the input range. common-mode rejection ratio over frequency poor layout can cause some of the common-mode signal to be converted to a differential signal before reaching the in-amp. this conversion can occur when the path to the positive input pin has a different frequency response than the path to the negative input pin. for best cmrr vs. frequency performance, the input source impedance and capacitance of each path should be closely matched. this includes connecting pin 1 to ?v s , which matches the parasitic capacitance and the leakage between the inputs and adjacent pins. place additional source resistance in the input path (for example, for input protection) close to the in-amp inputs to minimize their interaction with the parasitic capacitance from the printed circuit board (pcb) traces. driving the reference pin traditional instrumentation amplifier architectures require the reference pin to be driven with a low impedance source. in these architectures, impedance at the reference pin degrades both cmrr and gain accuracy. with the ad8420 architecture, resistance at the reference pin has no effect on cmrr. ad8420 +in ?in ref fb v out g = 1 + r2 + r ref r1 v ref r1 r2 r ref 09945-062 power supplies use a stable dc voltage to power the instrumentation amplifier. noise on the supply pins can adversely affect performance. for more information, see the psrr performance curves in figure 24 and figure 25 . place a 0.1 f capacitor as close as possible to each supply pin. as shown in figure 62 , a 10 f tantalum capacitor can be used farther away from the part. this capacitor, which is intended to be effective at low frequencies, can usually be shared by other precision integrated circuits. keep the traces between these integrated circuits short to minimize interaction of the trace parasitic inductance with the shared capacitor. figure 63. calculating gain with reference resistance resistance at the reference pin does affect the gain of the ad8420 , but if this resistance is constant, the gain setting resistors can be adjusted to compensate. for example, the ad8420 can be driven with a voltage divider as shown in figure 64 . r1 r2 ad8420 + v s +in ?in 0.1f 10f 0.1f 10f ?v s v out 09945-060 ad8420 +in ?in ref fb v out g = 1 + r2 + r3 || r4 r1 r1 r2 r3 r4 v s 09945-063 figure 64. using resistor divider to set reference voltage figure 62. supply decoupling, ref, and output referred to local ground
ad8420 data sheet rev. 0 | page 22 of 28 capacitively coupled +v s c r r c ?v s ad8420 1 f high-pass = 2 rc thermocouple +v s ?v s 10m ? ad8420 transformer +v s ?v s ad8420 correct v out v out thermocouple +v s ?v s ad8420 capacitively coupled +v s c c ?v s ad8420 transformer +v s ?v s ad8420 incorrect v out v out v out v out 09945-061 figure 65. creating an i bias path input bias current return path the input bias current of the ad8420 must have a return path to ground. when the source, such as a thermocouple, cannot provide a return current path, create one, as shown in figure 65 . radio frequency interference (rfi) all instrumentation amplifiers can rectify high frequency out-of- band signals. once rectified, these signals appear as dc offset errors at the output. high frequency signals can be filtered with a low-pass rc network placed at the input of the instrumentation amplifier, as shown in figure 66 . the filter limits the input signal bandwidth according to the following relationship: )2(2 1 c d diff ccr uency filterfreq c cm rc uency filterfreq 2 1 where c d t 10 c v out r1 r2 +in + v s ?v s c c 330pf 5% c c 330pf 5% 10f 10f c d 3300pf 0.1f 0.1f r 20k ? 1% r 20k ? 1% ad8420 ?in 09945-064 figure 66. suggested rf i suppression filter c d affects the differential signal and c c affects the common-mode signal. values of r and c c are chosen to minimize out of band rfi at the expense of reduced signal bandwidth. mismatch between the r c c at the positive input and the r c c at the negative input degrades the cmrr of the ad8420 . by using a value of c d that is at least one magnitude larger than c c , the effect of the mismatch is reduced and performance is improved. c .
data sheet ad8420 rev. 0 | page 23 of 28 output buffering the ad8420 is designed to drive loads of 20 k or greater but can deliver up to 10 ma to heavier loads at lower output voltage swings (see figure 42 ). if more output current is required, buffer the ad8420 output with a precision op amp. figure 67 shows the recommended configuration using the ada4692-2 as a single supply. this low power op amp can swing its output from 1 v to 4 v on a single 5 v supply while sourcing or sinking more than 30 ma of current. when using this configuration, the load seen by the ad8420 is approximately r1 + r2. r1 r2 +5 v ?v s +v s ?v s +v s 0.1f v out 0.1f ada4692-2 v in ad8420 v ref 09945-065 figure 67. output buffering because the ada4692-2 is a dual op amp, another op amp is now free for use as an active filter stage or to buffer another ad8420 output on the same pcb. figure 68 shows another suggestion for how to use this second op amp. in this circuit, the voltage from the wiper of a potentiometer is buffered by the ada4692-2 , allowing a variable level shift of the output. resistors above and below the potentiometer reduce the total range of the level shift but increase the precision. if the potentiometer were connected directly to the ref pin of the ad8420 , gain error would be introduced from the variable resistance. the potentiometer can be tuned in hardware or software, depending on the type of potentiometer chosen. for a list of digital potentiometers made by analog devices, inc., visit www.analog.com/digipots/ . r1 r2 +5 v 0.1f v out 0.1f ada4692-2 v in ad8420 ref r r cw w ccw s uggestion for second a mplifier: variable level shift without a ffecting gain 09945-066 figure 68. variable level shift
ad8420 data sheet rev. 0 | page 24 of 28 applications information ad8420 in electrocardiography (ecg) a high-pass filter is commonly used in ecg signal conditioning circuitry to remove electrode offset and motion artifacts. to avoid degrading the input impedance and cmrr of the system, this filtering is typically implemented after the instrumentation amplifier, which limits the gain that can be applied with the instrumentation amplifier. with a 3-op-amp instrumentation amplifier, gain is applied in the first stage. because of this, the electrode offset is gained and then must be removed afterward with a high-pass filter. in the ad8420 architecture, the offset can be accounted for in the input stage by unbalancing the transconductance amplifier at the ref and fb pins. in the steady state, the offset at the input is not gained to the output, and higher frequency signals can be gained and passed through. using the ad8420 in this way, the offset tolerance is nearly the differential input range of the part (1 v). figure 69 shows an ecg front end that applies a gain of 100 to the signal while rejecting dc and high frequencies. this circuit combines the ad8420 with the ad8657 , which is a low power, low cost, dual, precision cmos op amp. ?5v 8200pf 10m ? instrumentation amplifier g = +100 ad8420 +5v ?5v +5v 3.3 f ab c 09945-072 402k ? 200pf 200pf 2000pf 100k ? 100k ? +5v ?5v ad8657-2 ad8657-1 ref fb 100k ? 1k ? 200k ? 200k ? 0.015 f three-pole lpf, bessel response f c = 50hz integrator provides high-pass pole at 0.5hz 110k ? 0.022 f 500k ? figure 69. ad8420 in an ecg front end
data sheet ad8420 rev. 0 | page 25 of 28 classic bridge circuit figure 70 shows the ad8420 configured to amplify the signal from a classic resistive bridge. this circuit works in dual-supply mode or single-supply mode. typically, the same voltage that powers the instrumentation amplifier excites the bridge. connecting the bottom of the bridge to the negative supply of the instrumentation amplifier sets up an input common-mode voltage that is located midway between the supply voltages. the voltage on the ref pin can be varied to suit the application. for example, the ref pin is tied to the v ref pin of an analog-to-digital converter (adc) whose input range is (v ref v in ). with an available output swing on the ad8420 of (?v s + 100 mv) to (+v s ? 150 mv), the maximum programmable gain is simply this output range divided by the input range. + v s ?v s 0.1f 0.1f v out v ref v diff ad8420 09945-069 figure 70. classic bridge circuit 4 ma to 20 ma single-supply receiver the 80 a maximum supply current, input range that goes below ground, and low drift characteristics make the ad8420 a very good candidate for use in a 4 ma to 20 ma loop. figure 71 shows how a signal from a 4 ma to 20 ma transducer can be interfaced to the ad8420 . the signal from a 4 ma to 20 ma transducer is single-ended, which initially suggests the need for a simple shunt resistor to ground to convert the current to a voltage. however, any line resistance in the return path (to the transducer) adds a current-dependent offset error; therefore, the current must be sensed differentially. in this example, a 5 shunt resistor generates a differential voltage at the inputs of the ad8420 between 20 mv (for 4 ma in) and 100 mv (for 20 ma in) with a very low common-mode value. with the gain resistors shown, the ad8420 amplifies the 100 mv input voltage by a factor of 40 to 4.0 v. 09945-073 ad627 line impedance 4ma to 20ma 5 ? 4ma to 20ma transducer r2 = 97.6k ? r1 = 2.49k ? 0.1f 5 v ad8420 r2r1 g = 40 power supply + ? + ? 0.8v to 4.0v figure 71. 4 ma to 20 ma receiver circuit
ad8420 data sheet rev. 0 | page 26 of 28 outline dimensions compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 72. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding ad8420armz ?40c to +85c 8-lead mini small outline package [msop], tube rm-8 y3y ad8420armz-r7 ?40c to +85c 8-lead mini small outlin e package [msop], 7-inch tape and reel rm-8 y3y ad8420armz-rl ?40c to +85c 8-lead mini small outlin e package [msop], 13-inch tape and reel rm-8 y3y 1 z = rohs compliant part.
data sheet ad8420 rev. 0 | page 27 of 28 notes
ad8420 data sheet rev. 0 | page 28 of 28 notes ?2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09945-0-3/12(0)

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